VLSI Physical Design & STA test (Intermediate)

Sample questions

5 sample questions from the VLSI Physical Design & STA test, with the answers. Samples are taken out of the live test, so you will not meet these when you sit it.

1. Which of the following statements accurately describes via insertion rules in VLSI physical design?

   1. Via insertion rules are determined by design rules specified in the technology file (LEF) and are influenced by the layer stackup, via size, and the need to maintain electrical continuity and minimize resistance.
   2. Via insertion rules are determined by the netlist and do not take into account the technology file or layer stackup.
   3. Via insertion rules are based solely on the physical dimensions of the via and do not require any consideration of the technology file or layer stackup.
   4. Via insertion rules are automatically handled by the router and do not require any manual intervention or consideration of design rules.

   Answer: A. Via insertion rules are determined by design rules specified in the technology file (LEF) and are influenced by the layer stackup, via size, and the need to maintain electrical continuity and minimize resistance.

   Via insertion rules are based on the technology file (LEF) and are influenced by the layer stackup, via size, and the need to maintain electrical continuity and minimize resistance. The other options are either incorrect or unrelated to the actual rules governing via insertion.

2. What is the behavior of H-tree clock distribution in terms of clock skew and clock signal propagation?

   1. H-tree clock distribution is used to increase the power consumption of the clock tree by adding redundant clock buffers.
   2. H-tree clock distribution minimizes clock skew by ensuring that the clock signal reaches all sinks with equal delay, using a hierarchical structure that splits the clock signal into symmetrical branches.
   3. H-tree clock distribution is not used in modern VLSI design due to its high complexity and poor scalability.
   4. H-tree clock distribution maximizes clock skew by allowing the clock signal to reach different sinks at varying delays.

   Answer: B. H-tree clock distribution minimizes clock skew by ensuring that the clock signal reaches all sinks with equal delay, using a hierarchical structure that splits the clock signal into symmetrical branches.

   H-tree clock distribution is designed to minimize clock skew by splitting the clock signal into symmetrical branches, ensuring that the clock reaches all sinks with equal delay. This is achieved by maintaining a balanced structure, where each branch of the tree is of equal length and width, which helps to reduce clock skew and maintain uniform clock arrival times across the chip. Other options are incorrect because they do not accurately describe the behavior of H-tree clock distribution.

3. Which statement correctly describes a requirement for the Test Access Port (TAP) configuration in Design for Test (DFT)?

   1. The TAP must be connected to the core logic through a power rail to ensure proper test data access.
   2. The TAP must be connected to the core logic through a dedicated scan chain to ensure proper test data access.
   3. The TAP must be connected to the core logic through a dedicated power domain to ensure proper test data access.
   4. The TAP must be connected to the core logic through a global clock network to ensure proper test data access.

   Answer: B. The TAP must be connected to the core logic through a dedicated scan chain to ensure proper test data access.

   The Test Access Port (TAP) must be connected to the core logic through a dedicated scan chain to ensure that test data can be properly accessed and shifted into and out of the design. This ensures that the TAP is fully integrated with the scan chains, allowing for efficient test pattern application and response capture. Other options may be incorrect because they either misrepresent the TAP's role or fail to emphasize the need for a dedicated scan chain connection.

4. Which method is the standard configuration for the Test Access Port (TAP) in digital circuits, and is preferred over proprietary alternatives for its widespread adoption and compatibility with testing tools?

   1. JTAG (IEEE 1149.1) boundary scan
   2. Clock domain crossing
   3. Proprietary test access mechanisms
   4. Scan chain reordering

   Answer: A. JTAG (IEEE 1149.1) boundary scan

   The Test Access Port (TAP) configuration is commonly implemented using JTAG (IEEE 1149.1) boundary scan, which is a standardized method for testing and debugging integrated circuits. An alternative to JTAG is the use of proprietary test access mechanisms, but these are less common and not standardized. JTAG is preferred due to its widespread adoption, support for complex test patterns, and compatibility with various testing tools. Proprietary methods may be used in specific cases where customization is required, but JTAG is the standard for TAP configuration.

5. Which of the following statements correctly describes a method to verify the Test Access Port (TAP) configuration?

   1. The TAP configuration is only relevant during the physical design phase and not during testing.
   2. The TAP configuration must be verified using JTAG boundary scan tests to ensure correct functionality.
   3. The TAP configuration is irrelevant for test access and can be ignored during verification.
   4. The TAP configuration is automatically handled by the synthesis tool and does not require manual verification.

   Answer: B. The TAP configuration must be verified using JTAG boundary scan tests to ensure correct functionality.

   The Test Access Port (TAP) configuration must be verified using JTAG boundary scan tests to ensure that all TAP pins (TCK, TMS, TDI, TDO) are correctly connected and functional. This is critical for proper test access and debugging. Other options are incorrect because they either describe unrelated processes or do not directly relate to verifying the TAP configuration.