Advanced SystemVerilog & UVM test (Advanced)

Sample questions

5 sample questions from the Advanced SystemVerilog & UVM test, with the answers. Samples are taken out of the live test, so you will not meet these when you sit it.

1. What is the correct description of the behavior of UVM sequence pre/post callbacks?

   1. UVM sequence pre/post callbacks are triggered during the execution of the sequence, allowing users to insert custom code before or after the sequence's body is executed.
   2. UVM sequence pre/post callbacks are used to override the sequence's randomization constraints during execution.
   3. UVM sequence pre/post callbacks are only supported in virtual sequences and not in regular sequences.
   4. UVM sequence pre/post callbacks are used to modify the sequence item's data types dynamically during execution.

   Answer: A. UVM sequence pre/post callbacks are triggered during the execution of the sequence, allowing users to insert custom code before or after the sequence's body is executed.

   UVM sequence pre/post callbacks are used to execute custom code before or after the sequence's body is executed, which is useful for tasks such as setup or cleanup. This is different from other sequence-related features such as overriding or randomization, which are not directly related to callback behavior. The correct option clearly describes the behavior of pre/post callbacks, while the other options either describe unrelated features or provide incorrect information.

2. What happens during coverage-based simulation termination in UVM?

   1. The simulation will terminate when all coverage goals are met, as specified in the coverage plan.
   2. The simulation will terminate when all code coverage metrics reach 100%.
   3. The simulation will terminate automatically after a fixed number of test cases, regardless of coverage.
   4. The simulation will not terminate based on coverage goals; it only stops when all test cases are executed.

   Answer: A. The simulation will terminate when all coverage goals are met, as specified in the coverage plan.

   In coverage-driven verification, the simulation can be configured to terminate once all coverage goals defined in the verification plan are met. This ensures that the verification process stops once the required coverage has been achieved, optimizing simulation time and resource usage.

3. How are coverage points for fields in a sequence item defined and sampled in UVM?

   1. The coverage point for a field in a sequence item is defined using a covergroup within the sequence item class, and the field is sampled during the transaction.
   2. The coverage point for a field in a sequence item is defined in the testbench using a covergroup, and the field is sampled during the simulation.
   3. The coverage point for a field in a sequence item is defined in the sequence class using a covergroup, and the field is sampled during the sequence execution.
   4. The coverage point for a field in a sequence item is defined using the UVM factory, and the field is sampled during the factory creation process.

   Answer: A. The coverage point for a field in a sequence item is defined using a covergroup within the sequence item class, and the field is sampled during the transaction.

   To define coverage points for fields in a sequence item, a covergroup is created within the sequence item class. The covergroup samples the field during the transaction, ensuring that the coverage is collected correctly. Other options may suggest incorrect methods such as defining coverage points in the sequence class or using the factory to manage coverage, which are not the standard practices for defining coverage points for sequence item fields.

4. Which UVM sequencer arbitration mode ensures strict randomness in the order of sequences, making it suitable for scenarios requiring fair and unpredictable access to the sequencer?

   1. UVM_SEQ_ARB_WEIGHTED
   2. UVM_SEQ_ARB_STRICT_RANDOM
   3. UVM_SEQ_ARB_FIFO
   4. UVM_SEQ_ARB_STRICT_FIFO

   Answer: B. UVM_SEQ_ARB_STRICT_RANDOM

   UVM_SEQ_ARB_STRICT_RANDOM is the only arbitration mode that guarantees random order of sequences, ensuring fair access to the sequencer without any prioritization. Other options like FIFO or WEIGHTED do not provide this strict randomness, while STRICT_FIFO is deterministic and not random.

5. Which of the following accurately describes the correct structure and content of a verification plan?

   1. The verification plan must be written based on the specification, but it does not need to include checkers or exit criteria.
   2. The verification plan is only a document for the verification team and does not require measurable coverage goals or checkers.
   3. The verification plan is written based on the RTL and includes only code coverage goals.
   4. The verification plan must be written based on the specification, not the RTL, and must include measurable coverage goals, checkers, and exit criteria.

   Answer: D. The verification plan must be written based on the specification, not the RTL, and must include measurable coverage goals, checkers, and exit criteria.

   The verification plan is a document that maps the specification features to verification methods and includes measurable coverage goals, checkers, and exit criteria. It must be written based on the specification, not the RTL, to ensure that all required functionality is covered. This ensures that the verification process is comprehensive and aligned with the design's requirements.