Advanced VHDL test (Advanced)

Sample questions

5 sample questions from the Advanced VHDL test, with the answers. Samples are taken out of the live test, so you will not meet these when you sit it.

1. When is using IF-THEN-ELSE for combinatorial logic suitable, and when is it better to use a concurrent signal assignment instead?

   1. IF-THEN-ELSE is only suitable for sequential logic and not for combinatorial logic.
   2. IF-THEN-ELSE should never be used in combinatorial logic because it infers sequential elements.
   3. Using IF-THEN-ELSE in combinatorial logic is always the best choice for clarity.
   4. Using IF-THEN-ELSE in combinatorial logic is suitable when the logic is conditional and depends on specific signal values. However, for purely combinatorial logic without explicit conditionals, a concurrent signal assignment is preferred for clarity and synthesis efficiency.

   Answer: D. Using IF-THEN-ELSE in combinatorial logic is suitable when the logic is conditional and depends on specific signal values. However, for purely combinatorial logic without explicit conditionals, a concurrent signal assignment is preferred for clarity and synthesis efficiency.

   When designing combinatorial logic, the IF-THEN-ELSE construct is appropriate for conditional logic. However, if the logic is purely combinatorial and does not require explicit conditionals, a concurrent signal assignment is preferred. This approach ensures that all possible signal combinations are handled explicitly, reducing the risk of inadvertently inferring latches or complex logic structures.

2. In an FPGA design, how should I/O timing constraints be defined for external signals connected to the device?

   1. Use `create_clock` with a period to define I/O timing constraints.
   2. Use `set_false_path` to exclude I/O timing constraints from analysis.
   3. Use `set_clock_groups` to define I/O timing constraints.
   4. Use `set_input_delay` and `set_output_delay` with a reference clock to define I/O timing constraints.

   Answer: D. Use `set_input_delay` and `set_output_delay` with a reference clock to define I/O timing constraints.

   In FPGA design, I/O timing constraints are defined using `set_input_delay` and `set_output_delay` with a reference clock to ensure that the timing of signals entering and leaving the device is correctly analyzed. This is essential for meeting timing requirements in the presence of external components. Other options are incorrect because they either refer to clock domain crossing techniques (which are unrelated to I/O timing constraints) or describe incorrect usage of timing constraints (e.g., using `set_false_path` for I/O timing, which is not appropriate).

3. In a synthesis-friendly VHDL design, what is the correct approach to handling a case statement to avoid latch inference and ensure all possible values are covered?

   1. Use a case statement without a sensitivity list to avoid simulation/synthesis mismatches.
   2. Omit the 'when others' clause to allow the synthesis tool to infer the most optimal hardware.
   3. Use a case statement with a 'when others' clause that assigns a default value, but exclude it from the synthesis tool.
   4. Use a case statement with a default 'when others' clause to ensure all possible values are handled, preventing latch inference.

   Answer: D. Use a case statement with a default 'when others' clause to ensure all possible values are handled, preventing latch inference.

   A synthesis-friendly case statement must cover all possible values of the case expression to avoid latch inference. This is achieved by including a 'when others' clause, which ensures that no value is left unhandled. Omitting this clause can lead to latches being inferred, which is not desirable in synchronous designs. The other options describe incorrect or incomplete practices for writing synthesis-friendly case statements.

4. What is a correct behavior of the Xilinx Vivado constraint wizard regarding clock constraints for PLL/MMCM outputs?

   1. The Xilinx Vivado constraint wizard derives clock constraints for all clock domains manually.
   2. The Xilinx Vivado constraint wizard automatically derives clock constraints for PLL/MMCM outputs.
   3. The Xilinx Vivado constraint wizard only derives clock constraints for input clocks.
   4. The Xilinx Vivado constraint wizard does not support deriving clock constraints for PLL/MMCM outputs.

   Answer: B. The Xilinx Vivado constraint wizard automatically derives clock constraints for PLL/MMCM outputs.

   The Xilinx Vivado constraint wizard is designed to automatically derive clock constraints for PLL/MMCM outputs, ensuring that the generated clocks are properly timed and analyzed during the synthesis and implementation phases. This behavior helps reduce manual effort and ensures accurate timing closure.

5. Which of the following statements about VHDL generics is true?

   1. Generics can be set dynamically during runtime.
   2. Generics are only supported in VHDL-2008.
   3. Generics cannot be used with unconstrained ports.
   4. Generics must be static at elaboration.

   Answer: D. Generics must be static at elaboration.

   Generics in VHDL must be static at elaboration, meaning their values must be known at compile time. This is a key requirement for using generics in VHDL, as they are used to parameterize entities and architectures. The other options are incorrect because generics can be set per instance with `generic map`, they do not require a specific version of VHDL (they are supported in VHDL-2008 and earlier), and they can be used with unconstrained ports.