Advanced Verilog test (Advanced)

Sample questions

5 sample questions from the Advanced Verilog test, with the answers. Samples are taken out of the live test, so you will not meet these when you sit it.

1. Which of the following timing constraints is used to define the maximum allowable delay from the input port of a design to the clock edge of the first flip-flop in the design?

   1. set_multicycle_path
   2. set_output_delay
   3. create_clock
   4. set_input_delay

   Answer: D. set_input_delay

   The set_input_delay constraint is used in static timing analysis to define the maximum allowable delay from the input port of a design to the clock edge of the first flip-flop in the design. This constraint ensures that the input signal arrives in time for the first clock edge, preventing setup violations. The other options are not directly related to defining input delays. 'create_clock' is used to define clock signals, 'set_output_delay' defines the delay from the last clock edge to the output port, and 'set_multicycle_path' is used to define paths that take multiple clock cycles.

2. What is the primary purpose of clock enable signals in digital design?

   1. Clock enable signals are used to increase clock skew and improve timing closure.
   2. Clock enable signals are used to eliminate the need for clock domain crossing in asynchronous designs.
   3. Clock enable signals are used to synchronize asynchronous signals across clock domains.
   4. Clock enable signals are used to gate the clock signal and reduce dynamic power consumption by disabling clocking to idle registers.

   Answer: D. Clock enable signals are used to gate the clock signal and reduce dynamic power consumption by disabling clocking to idle registers.

   Clock enable signals are used to gate the clock signal and reduce dynamic power consumption by disabling clocking to idle registers. This is a common practice in low-power design to minimize unnecessary toggling of clock signals. Other options are incorrect because clock enable signals do not increase clock skew, do not eliminate the need for clock domain crossing, and are not used to synchronize asynchronous signals.

3. What is the primary purpose of clock buffer insertion in digital design?

   1. Clock buffer insertion is a method of clock division to generate multiple clock signals with different frequencies.
   2. Clock buffer insertion is used to improve signal integrity in high-speed serial communication links.
   3. Clock buffer insertion is used to reduce skew between clock signals in a design by replicating the clock signal and distributing it to different parts of the circuit.
   4. Clock buffer insertion is primarily used for power optimization in low-power designs.

   Answer: C. Clock buffer insertion is used to reduce skew between clock signals in a design by replicating the clock signal and distributing it to different parts of the circuit.

   Clock buffer insertion is a technique used to minimize clock skew by replicating the clock signal and distributing it to various parts of the design. This helps ensure that the clock signal reaches all flip-flops and sequential elements with minimal delay variation, which is crucial for timing closure. Other options are incorrect because they describe unrelated concepts such as power optimization, signal integrity, or clock division.

4. Which of the following statements correctly describes the use cases for power domain isolation with isolation cells and retention registers versus power domain isolation with level shifters?

   1. Power domain isolation with isolation cells and retention registers is preferred for power domains that require frequent power state transitions, while power domain isolation with level shifters is used when multiple voltage domains are involved.
   2. Power domain isolation with isolation cells and retention registers is preferred for power domains that require frequent power state transitions, while power domain isolation with level shifters is used for domains that do not require power state transitions.
   3. Power domain isolation with level shifters is preferred for power domains that require frequent power state transitions, while power domain isolation with isolation cells and retention registers is used when multiple voltage domains are involved.
   4. Power domain isolation with level shifters is preferred for power domains that require frequent power state transitions, while power domain isolation with isolation cells and retention registers is used for domains that do not require power state transitions.

   Answer: A. Power domain isolation with isolation cells and retention registers is preferred for power domains that require frequent power state transitions, while power domain isolation with level shifters is used when multiple voltage domains are involved.

   Power domain isolation with isolation cells and retention registers is suitable for domains that need to be turned on and off frequently, as they manage the stable transfer of data between power states. Power domain isolation with level shifters is used when multiple voltage domains are involved, ensuring proper signal level conversion between different voltage levels.

5. In a realistic project scenario involving clock domain crossing, which of the following is the correct application of CDC assertion-based verification?

   1. Use CDC assertions to verify that all clock signals are properly gated for power savings.
   2. Use CDC assertions to enforce that all control signals are implemented using asynchronous resets.
   3. Use CDC assertions to verify that all data signals are properly synchronised across domains using two-flop synchronisers.
   4. Use CDC assertions to automatically insert two-flop synchronisers for all multi-bit data signals.

   Answer: C. Use CDC assertions to verify that all data signals are properly synchronised across domains using two-flop synchronisers.

   CDC assertion-based verification ensures that data signals are correctly synchronised across clock domains. Using two-flop synchronisers is the standard method for single-bit signals, and CDC assertions can automatically check that this is implemented. Other options are either incorrect or unrelated to CDC assertion-based verification.