Manoj Kumar
Design Verification Engineer| VLSI | Formal Verification
Hyderabad
About
I am a Design Verification Engineer at Tata Consultancy Services with 1.6 years of experience in protocol verification, including PCIe Gen4, AXI4, DDR4, and UCIe. I specialize in SystemVerilog, UVM, and SVA, and have developed Python and Tcl scripts to improve regression efficiency and debugging. My work has led to faster test execution, accurate coverage reporting, and the identification and resolution of critical bugs in hardware designs. I am looking to advance my career as a VlSI Front end Engineer, leveraging my strong skills in constrained random testing, functional coverage, and verification methodologies.
Experience
Design Verification Engineer
April 2025 – PresentTata Consultancy Services (TCS)
Run 150 regression tests on every new VIP version. Trace each failure to its cause and log it in an Excel sheet. Fixed a coverage report that showed 0% after merging 86 regression runs. The cause was a version mismatch between Xcelium 22.09 and IMC 22.03. Fixed it with IMC Tcl commands that load the runs and report without saving a merged database. Wrote Python scripts to read simulation logs and find failing tests and their reasons quickly. Wrote 30+ constrained-random and directed tests for LTSSM state rules and power-management handshakes. Checked results against waveforms and the UCIe link register. Wrote SystemVerilog Assertions for protocol rules and timing. Used waveforms and logs to find and fix issues. Built a CRC8 check in the Adapter layer agent. Raised sideband coverage by writing directed tests for uncovered bins. Connected the UCIe VIP to AXI master and slave agents and verified it with constrained-random tests.
Education
National Institute of Technology, Durgapur
2024B.Tech, Electronics and Communication Engineering · Grade: 8.1
Projects
Chromite M SoC – RISC-V Peripheral Verification
C, RISC-V, SPI, UART, GPIO, QSPI, PWM
Wrote C tests for SPI, UART, GPIO, QSPI and PWM. Watched the bus traffic and checked results against waveforms.
I2C Master and Slave Verification
UVM, I2C, OBI
Built a UVM environment for an OBI-driven I2C master and slave. Found and fixed a START/STOP timing race.
DDR4 and ST-MRAM Integration
Tcl, Xilinx DDR4 MIG, Everspin ST-MRAM, Vivado
Fitted an Everspin ST-MRAM model to a Xilinx DDR4 MIG controller in Vivado, using Tcl scripts. Found seven testbench bugs and one model bug.
PCIe UVM Testbench – Xilinx PCIe Gen4 IP
UVM, PCIe, BFM, UCIe
Built a UVM testbench that connects a PCIe BFM into a UCIe setup. Wrote a scoreboard with six checks and a sequence library with 10 test groups.
UCIe VIP Verification
SystemVerilog, UVM, Constrained Random, Directed Tests
Wrote 30+ constrained-random and directed tests for LTSSM state rules and power-management handshakes. Checked results against waveforms and the UCIe link register.
Skills
Achievements
Fixed Coverage Report Mismatch
2025Fixed a coverage report that showed 0% after merging 86 regression runs. The cause was a version mismatch between Xcelium 22.09 and IMC 22.03. Fixed it with IMC Tcl commands that load the runs and report without saving a merged database.
Improved Sideband Coverage with Directed Tests
2025Built a CRC8 check in the Adapter layer agent. Raised sideband coverage by writing directed tests for uncovered bins.
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